In recent years, along with development of semiconductor manufacturing technology, the number of electrodes (the number of terminals) of a semiconductor element (semiconductor chip) included in a main portion of a semiconductor device such as an LSI is increasing, and thus, in an electrode arranged in a periphery of the semiconductor element, a trend toward a fine pitch (narrow pitch) electrode is progressing. For this reason, a flip chip connection technology is used widely instead of a method of a related art in which each electrode and an outside member (such as an electrode on a substrate) are electrically connected by wire bonding. In this flip chip connection technology, not only the peripheral part of the semiconductor element but also the whole plane part is utilized, and the electrodes are arranged in a form of an area array so that the number of electrodes may increase significantly without using a fine pitch electrode. Each electrode and an outside member are electrically connected directly using these area-array arranged electrodes.
Further increase of the number of electrodes has been required also in a semiconductor element included in a semiconductor device of the flip chip connection type. As a result, in order to support a fine pitch electrode, the number of layers in a substrate has been increased. For this reason, a number of manufacturing processes has increased, and introducing a special material or the like has become necessary, thereby a manufacturing yield declines.
In the case of a semiconductor device of a multi-chip type in which a plurality of semiconductor elements are mounted on a substrate by a flip chip connection, further scaling down of dimensions is required for the substrate. In this semiconductor device, due to increase of the number of electrodes, the number of connection points between the electrodes and outside members increases. Not only that, scaling down of dimensions of a bump (projection-shaped electrode), which undertakes a role of: electrically connecting an electrode of a semiconductor element and an electrode arranged on the substrate corresponding to the electrode of the semiconductor; and keeping an interval between the semiconductor element and the substrate at a predetermined distance, is inevitable. In order to make a gap between the semiconductor element and the substrate narrower, a small sized (low height) bump is needed. The cost increases due to a small sized bump.
FIG. 13 indicates a sectional view of a semiconductor device 100 of a flip chip connection type according to a first related technology. As shown in FIG. 13, in the semiconductor device 100, a semiconductor element 102 having a first electrode 101, arranged on its one main surface, for electrically connecting to an outside member, is mounted on a substrate 104 having a second electrode 103 arranged on it corresponding to the first electrode 101 so that the first electrode 101 and the second electrode 103 are electrically connected via a bump 105.
In order to protect a connecting point, such as the electrode 101 and 103 from the surrounding atmosphere, a sealing body 106 is formed by resin filling. An external electrode 107 is arranged on the back of the substrate 104 so as to be electrically connected to the second electrode 103. A bump 108 is electrically connected to the external electrode 107. FIG. 14 indicates a sectional view of a multi-chip type semiconductor device 200 by a flip chip connection according to the second related technology. In the semiconductor device 200, as shown in FIG. 13, two of semiconductor elements 102A and 102B are mounted on the common substrate 104 in approximately the same structure as FIG. 13.
However, in these flip chip connection type semiconductor devices as above, there are several problems. First, by the fine pitch electrode of the semiconductor element, the height of the bump also becomes low, and a gap between the semiconductor element and the substrate becomes small. Filling cleaning solution or the like into this gap becomes difficult. For this reason, due to deterioration of the flux detergency, degradation of a UF (underfill) resin filling property or the like, the productivity declines. In addition, according to the increase of the number of connection points due to increase of the number of the electrodes, a connection yield for the electrodes declines. Further, compared with the dimensional scaling down of the electrode and the bump of the semiconductor element, scaling down of the substrate requires higher technology. That is, in processing the semiconductor element, silicon with a high flatness is used as a substrate material, and a manufacturing apparatus has high accuracy. On the other hand, in processing the substrate, metal wiring is formed on a base material of resin or glass cloth saturated with resin or the like. As has been mentioned above, in order to dimensionally scale down the substrate, increase of the number of processes by the high multilayering, introduction of the special material and degradation of the manufacturing yield according to them cannot be avoided. For this reason, the cost becomes high. In addition, for the semiconductor device of the multi-chip type on which the plurality of semiconductor elements are mounted, because further scaling down is required, the cost of the substrate becomes yet higher.
On the other hand, in order to speed up for the semiconductor device and reduce a burden on the semiconductor element, there is disclosed a semiconductor device in which a semiconductor element is flip-chip connected on a substrate via an interposer including a semiconductor substrate on which an active element is formed (patent document 1). However, in this semiconductor device, because a semiconductor substrate of such as silicon is used, although the interposer substrate is advantageous for scaling down, scaling down a connection section between the interposer substrate and a base board is difficult. In addition, in the interposer substrate, in order to connect to the base board, wiring needs to be formed on the back of the interposer substrate. Formation of penetration wiring to the semiconductor substrate requires high cost. For this reason, there is also a drawback that the cost of the interposer substrate becomes high. Further, because an active element is formed on this interposer substrate, there is a shortcoming such that the manufacturing steps increases, thereby the cost up becomes inevitable.
Also disclosed is a semiconductor device in which, in order to increase the number of signals inputted between a chip and a substrate without increasing the area of the chip and the substrate, a chip having first inductor conductors formed corresponding to a part of input-output terminals is mounted on a substrate having second inductor conductors formed corresponding to the first inductor conductors and external connection terminals formed corresponding to the second inductor conductors (patent document 2). The first and second inductor conductors are magnetically coupled, and a signal is transmitted by the electromagnetic induction between the chip and the substrate.
Further, there is disclosed a semiconductor device having a plurality of semiconductor chips, each having an inductor for communication, being laminated and being inductor-connected to each other, wherein, in order to prevent decline of a magnetic field strength of an inductor due to an eddy current generated in a chip, the semiconductor device includes: a semiconductor layer arranged on a semiconductor substrate having a first resistivity, the semiconductor layer having a second resistivity smaller than the first resistivity; a wiring layer on this semiconductor layer; and an inductor, provided in this wiring layer, for performing sending and receiving a signal (patent document 3).